Characterization of 4H-SiC Piezoresistive/CMOS Stress Sensors

Conventional silicon piezoresistive/CMOS stress sensors are limited to a maximum 150˚C operating temperature due to the relatively low bandgap voltage of silicon (1.1eV).

We have designed 4H-SiC piezoresistive and CMOS stress sensors capable of high-temperature in-situ die stress mapping for evaluating the reliability of different packaging/assembly technologies. These on-chip stress sensors are compatible with standard CMOS readouts and can operate at elevated temperatures in harsh environments thanks to the high bandgap energy of 4H-SiC (3.23eV).

Assignment

The student will perform the assignment at ECTM:

• Duration: ~9 months.
• Location: Measurement lab and EKL facilities.
• Collaboration with NXP/IMEC might be required for mechanical test set-up preparation (4PB machine).

The expected activities to be carried out by the student are:

• Preparing wafer strip samples (gluing and bonding to flex-PCB).
• Preparing the electrical setup for mechanical tests.
• Extraction of piezoresistive coefficients of 4H-SiC VDP sensors.

Requirements

You are an ambitious student looking for a challenging thesis project on a sensor characterization and optimization problem. You have a physics, or microelectronics background and an interest in hands-on experiences and electronic measurement setups. Experience with running scripts in LabVIEW is highly recommended. Good communication skills in English and a pro-active attitude are expected.

Contact

Last modified: 2022-04-11